The need and application for clock generation is ubiquitous. Clock generation may be accomplished using phase-locked loop (PLL) circuitry. PLL circuitry generally takes a reference signal, such as a system clock, compares it to a feedback signal, and generates an error signal in response thereto. The error signal drives a voltage controlled oscillator (VCO) that produces an output clock signal. The output clock signal is also scaled (typically with a divider) to generate the feedback signal for comparison with the reference signal. The divisor setting of the divider sets the frequency ratio between the reference and output clock signals. For example, if the divisor is set to three, the output clock signal will have a frequency 3 times the frequency of the reference signal.
PLL circuitry may eliminate or substantially reduce temporal skew between the reference signal and the output signal with proper phase comparator design. Eliminating skew is critical in applications such as, but not limited to, I/O interface timing specifications of a modern microprocessor.
In recent years, the clock distribution delay (and thus the PLL feedback delay) has increased while the PLL reference frequency is rising. Both of these factors may result in degraded PLL performance. Additionally, the clock distribution may exceed a few output clock cycles in delay. Other structures may be added in series with the clock distribution to contribute to a longer feedback loop delay. These may include clock stretch/shrink DFT, modulation of clock sensitivity to power supply, PLL phase-frequency detector output filtering (“chopping”), etc.
One method to alleviate the problem of the increased clock distribution delay is to lower the reference frequency of the PLL circuit. However, this results in high synthesis ratios, which may necessitate a large filter capacitor. Another method may allow for the destination internal clock to be misaligned from the external reference. However, this may occur at the expense of tighter timing margins across clock domains or require asynchronous timing transfer.